1. Field of the Invention
The present invention relates to a bonding method of semiconductor substrates to perform three-dimensional mounting by bonding plural semiconductor substrates through an interlayer adhesive, and to a laminated structure fabricated thereby.
2. Description of the Related Art
A reduction in the thickness and size of electronic devices has been achieved by miniaturizing the components mounted thereon. The miniaturization of electronic devices has been largely dependent on the fine processing technology of LSI. However, introduction of more advanced fine processing technology into the LSI process requires significant capital investment, which is against the need for product cost reduction. In order to solve this technical problem, there has been developed a technology of mounting in a three-dimensional direction (three-dimensional mounting), instead of mounting in a plane direction (two-dimensional mounting) as in the past. This is accomplished by forming through-hole electrodes in a direction perpendicular to a surface of a silicon wafer, forming electrodes on the front and back surfaces of the silicon wafer, and electrically coupling the electrodes together to laminate the silicon wafer.
There have been proposed processes for forming a semiconductor device by three-dimensional lamination in JP-A No. 136187/2005 and its counterpart European Patent Application Publication: EP 1686623 A1, and in JP-A No. 183580/2005 and its counterpart United States Patent Application Publication No. US 2005/0136568 A1 and the registered U.S. Pat. No. 7,109,060 thereof. However, in the above cited documents, there is no detailed description with respect to the lamination about whether wafers are simultaneously laminated, or the wafers are cut into individual chips before being laminated.
The following processes are proposed as a method for simultaneously laminating wafers.
In JP-A No. 319707/2004 and its counterpart United States Patent Application Publication: No. US 2004/0207082 A1, there is provided a process for simultaneously fabricating plural semiconductor packages at wafer level, followed by cutting into individual semiconductor packages. The semiconductor package has a laminated structure in which two or more semiconductor devices are bonded together through an insulation layer. The semiconductor devices, each including a substrate and device patterns formed on a surface thereof, are laminated in such a manner that the device pattern surface of the lower semiconductor device faces the non-device pattern surface of the upper semiconductor device.
In JP-A No. 302858/2005, there is provided a process for coupling electrodes of two different wafers by superimposing the wafers on one another. This process has a problem of being unable to bring all electrodes on one wafer, into contact with corresponding electrodes on the other wafer, due to wafer deformation caused by foreign material on a wafer holder or due to irregularities although there is no foreign material. In order to solve such a problem, a wafer holding surface of the wafer holder is divided into plural holding areas, to control the force of sucking a wafer as well as the force of pressing the wafer against the other wafer independently in each of the holding areas. In this way, it is possible to suck a wafer in one holding area, while pressing the wafer against the other wafer in another holding area. Thus, a uniform bonding can be obtained regardless of wafer surface irregularities.
In JP-A No. 100656/2006, there is provided a process for fabricating a lamination-type semiconductor device by laminating wafers, in which marks on the wafers to be superimposed on one another are detected to align between the wafers. At this time, when the wafer having been laminated is observed, plural alignment marks come into sight on the wafer, and the detection accuracy decreases. This leads to a decrease of alignment accuracy, resulting in a low production yield of lamination-type semiconductor devices. Thus, it is desired to form alignment marks being spaced apart at a predetermined distance on the wafers adjacent to each other when laminated. In this way, even when plural alignment marks come into sight, the alignment marks can be easily separated from each other.
In JP-A No. 249620/2003, there is provided a bonding method of semiconductor, and a laminated semiconductor fabricated by the method that prevents undesirable behavior of surface coating resin when bonding semiconductors, especially wafers, to ensure bonding of the metal electrodes, and preferably to ensure bonding of the entire surfaces to be bonded without forming void(s) therebetween at low temperature. More specifically, it is desired to bond semiconductors each having a surface on which electrodes are exposed, by filling resin between the electrodes of at least one of the semiconductors to form a resin layer on the surface thereof, projecting the electrodes of at least one of the specific semiconductors from the surface thereof, applying a pressure to the semiconductors with their electrodes brought into contact with each other to extend the contact portion of the electrodes, and bring the surface of the resin layer into contact with the surface of the other semiconductor.